[ARCHIVED] ECE 2372 Capstone Project
- Verilog 100%
| traffic | ||
| verilog | ||
| README.md | ||
| slides.pptx | ||
ECE 2372: Modern Digital System Design Capstone
Overview
This repository contains the code to the verilog project, as well as the images and video evidence of the work we have already done.
Hardware Project Criteria: here
Software Project Criteria: here
Repository Layout
Here is the layout of the repository:
ECE 2372 CAPSTONE
──────────────────
├── slides.pptx <- the slides in powerpoint form
├── README.md <- readme file
├── verilog <- verilog project
│ ├── waveform/ <- folder containing the waveform graphs
│ ├── inctop.v <- the final top module of the project
│ └── testbench.v <- the testbench to the verilog file
└── traffic <- folder containing all of the files regarding the traffic light
├── photos/ <- photos
├── k_maps/ <- k maps, including the templates
├── circuitjs.txt <- circuitjs circuit (https://www.falstad.com/circuit/circuitjs.html)
└── traffic_light.vcb <- visual circuit board circuit
Traffic Project
Traffic lights gif:
Traffic lights gif 2:
Verilog Project
Final waveform:
